This application claims the benefit of Korean Patent Application No. 2000-82094, filed on Dec. 26, 2000, under 35 U.S.C. xc2xa7119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a first-in first-out (FIFO) memory device and a method of generating a flag signal in the same.
2. Description of Related Art
In communication between different processors (or systems) having different data rates, there generally exists a difference between the speed at which one processor (or system) writes data and the speed at which the other processor (or system) reads data. The first-in first-out (FIFO) memory device is used to control data transmission between different processors having different data rate.
FIG. 1 is a block diagram illustrating data transmission between processors according to conventional art. Processors 10 and 12 and a FIFO memory device 14 are shown. As shown in FIG. 1, the processor 10 transfers input data IN to the FIFO memory device 14, and the processor 12 receives data from the FIFO memory device 14 to output data OUT. The processor 10 is faster in data rate than the processor 12.
The FIFO memory device 14 is reset in response to a reset signal output from the processor 10 and is enabled in response to a write enable signal WEB transferred from the processor 10 and stores write data WD in response to a write clock signal WCK. If the FIFO memory device 14 becomes full, the FIFO memory device 14 transfers a full flag signal Full to the processor 10 so that the processor 10 cannot write data. Also, the FIFO memory device 14 is enabled in response to a read enable signal REB transferred from the processor 12 and transfers read data RD to the processor 12 in response to a read clock signal RCK. If the FIFO memory device 14 becomes empty, the FIFO memory device 14 transfers an empty flag signal Empty to the processor 12 so that the processor 12 cannot read data.
The FIFO memory device 14 of FIG. 1 is configured to be reset in response to the reset signal output from the processor 10 but may be configured to be reset in response to a reset signal applied from another controller (not shown) other than the processors 10 and 12.
As described above, the FIFO memory device 14 is arranged between the two processors 10 and 12 to facilitate data transfer between the different processors having different data rates.
FIG. 2 is a block diagram illustrating a configuration of the FIFO memory device of FIG. 1. As shown in FIG. 2, the FIFO memory device includes a dual port memory cell array 20, a write pulse generating circuit 22, a write address generating circuit 24, a write data register 26, a read pulse generating circuit 28, a read address generating circuit 30, a read data register 32, and a flag generating circuit 34.
The dual port memory cell array 20 writes data in response to a write address WA and reads data in response to a read address RA. The write pulse generating circuit 22 generates an internal write clock signal iWCK in response to an inverted write enable signal WEB and a write clock signal WCK when the full flag signal Full is not active. The write address generating circuit 24 is reset in response to the reset signal and generates a write address WA in response to the internal write clock signal iWCK. The write data register 26 stores write data WD in response to the internal write clock signal iWCK to output it to the dual port memory cell array 20. The read pulse generating circuit 28 generates an internal read clock signal iRCK in response to an inverted read enable signal REB and a read clock signal RCK when the empty flag signal Empty is not active. The read address generating circuit 30 is reset in response to the reset signal and generates a read address RA in response to an internal read clock signal iRCK. The read data register 32 outputs read data RD output from the dual port memory cell array 20 in response to the internal read clock signal iRCK. The flag generating circuit 34 compares a write address WA with a read address RA in response to the reset signal, and generates a full flag signal Full in response to an internal write clock signal iWCK and generates an empty flag signal Empty in response to an internal read clock signal iRCK when a write address WA and a read address RA are equal.
FIG. 3 is a circuit diagram illustrating a configuration of the dual port memory cell array of FIG. 2. The dual port memory cell array includes an m_n-number of memory cells MC connected, respectively, between an n-number of write word lines wwl1 to wwln and an m-number of write bit line pairs wbl1 and wbl1 b to wblm and wblmb, and between an n-number of read word lines rwl1 to rwln and an m-number of read bit line pairs rbl1 and rbl1b to rblm and rblmb.
As shown in FIG. 3, each of the memory cells MC includes NMOS transistors N1 and N2 for a write data transmission, NMOS transistors N3 and N4 for a read data transmission and a latch LA1 having inverters I1 and I2 for a data latch.
The NMOS transistors N1 and N2 transfer data of the write bit line pairs wbl1 and wbl1b to wblm and wblmb to nodes n1 and n2 in response to a signal transferred to the write word lines wwl1 to wwln, respectively. The NMOS transistors N3 and N4 transfer data of the nodes n1 and n2 to the read bit line pairs rbl1 and rbl1b to rblm and rblmb in response to a signal transferred to the read word lines rwl1 to rwln, respectively. The latch LA1 latches data of the nodes n1 and n2.
FIG. 4 is a circuit diagram illustrating a configuration of the write address generating circuit of FIG. 2. The write address generating circuit includes a column address generating circuit 40 and a row address generating circuit 42. The column address generating circuit 40 includes n-bit serial sequential shift registers WCA0 to WCA(nxe2x88x921), and the row address generating circuit 42 includes m-bit serial sequential shift registers WRA0 to WRA(mxe2x88x921).
The n-bit serial sequential shift registers WCA0 to WCA(nxe2x88x921) include a register WCA0 and registers WCA1 to WCA(nxe2x88x921). The register WCA0 includes a master portion having a CMOS transmission gate C1, an NMOS transistor NM1 and a latch LA2 having inverters I3 and I4, and a slave portion having a CMOS transmission gate C2 and a latch LA3 having inverters I5 and I6. Each of the registers WCA1 to WCA(nxe2x88x921) includes a master portion having a CMOS transmission gate C3, a PMOS transistor PM1 and a latch LA4 having inverters I7 and I8 and a slave portion having a CMOS transmission gate C4 and a latch LA5 having inverters I9 and I10.
The m-bit serial sequential shift registers WRA0 to WRA(mxe2x88x921) include a register WRA0 having the same configuration as the register WCA0, and registers WRA1 to WRA(mxe2x88x921) having the same configuration as the registers WCA1 to WCA(nxe2x88x921).
The write address generating circuit further includes inverters I11 and I12, and a control circuit 44. The inverter I11 inverts an internal write clock signal iWCK to control the CMOS transmission gates C1 to C4 of the n-bit serial sequential shift registers WCA0 to WCA(nxe2x88x921). The inverter I12 inverts a reset signal to control the NMOS transistor NM1 and the PMOS transistor PM1 of the shift registers WCA0 to WCA(nxe2x88x921) and WRA0 to WRA(mxe2x88x921). The control circuit 44 generates a control signal to control the CMOS transmission gates C1 to C4 of the m-bit serial sequential shift registers WRA0 to WRA(mxe2x88x921).
Operation of the write address generating circuit of FIG. 4 is described in accordance with the following. The PMOS transistor PM1 and the NMOS transistor NM1 of the n-bit serial sequential shift registers WCA0 to WCA(nxe2x88x921) and the m-bit serial sequential shift registers WRA0 to WRA(mxe2x88x921) are turned on when a reset signal having a logic xe2x80x9chighxe2x80x9d level is applied. The latches LA2 and LA4 invert and latch signals transferred from the PMOS transistor PM1 and the NMOS transistor NM1 to generate a sequence xe2x80x9c10 . . . 0xe2x80x9d to write master column and row addresses wmca0 and wmca(nxe2x88x921) to wmra0 and wmra(nxe2x88x921). The CMOS transmission gates C2 and C4 of the n-bit serial sequential shift registers WCA0 to WCA(nxe2x88x921) are turned on when the internal write clock signal iWCK is transited from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level to transfer write slave column addresses wsca(nxe2x88x921) and wsca0 to wsca(nxe2x88x922) to the latches LA2 and LA4, respectively. Each of the latches LA2 and LA4 inverts and latches output signals of the CMOS transmission gates C1 and C3 to generate the write master column addresses wmca0 to wmca(nxe2x88x921). The CMOS transmission gates C1 and C3 are turned on when the internal write clock signal is transited from a logic xe2x80x9chighxe2x80x9d level to a logic xe2x80x9clowxe2x80x9d level to transfer the write master column addresses wmca0 to wmca(nxe2x88x921) to the latches LA3 and LA5, respectively. Each of the latches LA3 and LA5 inverts and latches output signals of the CMOS transmission gates C2 and C4 to generate the write slave column addresses wsca0 to wsca(nxe2x88x921).
That is, the n-bit serial sequential shift registers WCA0 to WCA(nxe2x88x921) reset the write master column addresses wmca0 to wmca(nxe2x88x921) to xe2x80x9c10 . . . 0xe2x80x9d in response to a reset signal. And, whenever the internal write clock signal iWCK is transited from a logic xe2x80x9clowxe2x80x9d level to a logic xe2x80x9chighxe2x80x9d level, the write master column addresses wmca0 to wmca(nxe2x88x921) are shifted by a 1-bit and are changed from xe2x80x9c01 . . .0xe2x80x9d to xe2x80x9c00 . . . 1xe2x80x9d. Consequently, the n-bit serial sequential shift registers WCA0 to WCA(nxe2x88x921) repeatedly perform a shifting operation of from xe2x80x9c10 . . . 0xe2x80x9d to xe2x80x9c00 . . . 1xe2x80x9d.
The m-bit serial sequential shift registers WRA0 to WRA(mxe2x88x921) perform the same operation as the n-bit serial sequential shift registers WCA0 to WCA(nxe2x88x921). However, the m-bit serial sequential shift registers WRA0 to WRA(mxe2x88x921) perform a shifting operation in response to an output signal of the control circuit 44 instead of the internal clock signal iWCK of the CMOS transmission gates C1 to C4. When the write slave column address wsca(nxe2x88x921) is xe2x80x9c1xe2x80x9d, an output signal of the control circuit 44 becomes xe2x80x9c0xe2x80x9d, so that the control circuit 44 does not perform a shifting operation. However, when the write slave column address wsca(nxe2x88x921) is xe2x80x9c0xe2x80x9d, an output signal of the control circuit 44 becomes xe2x80x9c1xe2x80x9d, so that the control circuit 44 performs a shifting operation. That is, the m-bit serial sequential shift registers WRA0 to WRA(mxe2x88x921) perform a shifting operation when a carrier is generated from the column address generating circuit 40, but do not perform a shifting operation when a carrier is not generated from the column address generating circuit 40.
The write master column addresses wmca0 to wmca(nxe2x88x921) generated from the write address generating circuit of FIG. 4 are used as signals to select the write bit line pairs wbl1 and wbl1b to wblm and wblmb of the dual port memory cell array of FIG. 3 and are used as signals to select the write word lines wwl1 to wwln of the dual port memory cell array of FIG. 3 by the write master row addresses wmra0 to wmra(mxe2x88x921).
FIG. 5 is a circuit diagram illustrating the read address generating circuit of FIG. 2. The read address generating circuit of FIG. 5 has a similar configuration to that of the write address generating circuit of FIG. 4. Reference numeral 50 represents a column address generating circuit, and the column address generating circuits 40 and 50 of FIGS. 4 and 5 perform analogous operations. Reference numeral 52 represents a row address generating circuit, and the row address generating circuits 42 and 52 of FIGS. 4 and 5 perform analogous operations. References RCA0 to RCA(nxe2x88x921) represent n-bit serial sequential shift registers, and the n-bit serial sequential shift registers WCA0 to WCA(nxe2x88x921) and RCA0 to RCA(nxe2x88x921) of FIGS. 4 and 5 perform analogous operations. References RRA0 to RRA(mxe2x88x921) represent m-bit serial sequential shift registers, and the m-bit serial sequential shift registers WRA0 to WRA(mxe2x88x921) and RRA0 to RRA(mxe2x88x921) perform analogous operations. A reference iRCK represents an internal read clock signal, and the internal read clock signal iRCK substitutes for the internal write clock signal iWCK of FIG. 4. References rmca0 to rmca(nxe2x88x921) and rmra0 to rmra(mxe2x88x921) represent read master column and row addresses, respectively, and the read master column and row addresses rmca0 to rmca(nxe2x88x921) and rmra0 to rmra(mxe2x88x921) substitute for the write master column and row addresses wmca0 to wmca(nxe2x88x921) and wmra0 to wmra(mxe2x88x921).
As described above, the read address generating circuit of FIG. 5 operates in a similar manner to the write address generating circuit of FIG. 4. Therefore, description of its operation is omitted to avoid redundancy.
The read master column addresses rmca0 to rmca(nxe2x88x921) generated from the read address generating circuit of FIG. 5 are used as signals to select the read bit line pairs rbl1 and rbl1 b to rblm and rblmb of the dual port memory cell array of FIG. 3 and are used as signals to select the read word lines rwl1 to rwlm of the dual port memory cell array of FIG. 3 by the read master row addresses rmra0 to rmra(mxe2x88x921).
FIG. 6 is a block diagram illustrating the flag generating circuit of FIG. 2. The flag generating circuit of FIG. 6 includes a comparison circuit 60 and a flag signal generating circuit 62. The comparison circuit 60 compares the write master column and row addresses wmca0 to wmca(nxe2x88x921) and wmra0 to wmra(mxe2x88x921) with the read master column and row addresses rmca0 to rmca(nxe2x88x921) and rmra0 to rmra(mxe2x88x921), and generates a control signal CO when the write master column and row addresses wmca0 to wmca(nxe2x88x921) and wmra0 to wmra(mxe2x88x921) and the read master column and row addresses rmca0 to rmca(nxe2x88x921) and rmra0 to rmra(mxe2x88x921) become equal. The flag signal generating circuit 62 generates a full flag signal Full when the control signal CO is generated in response to the internal write clock signal iWCK and generates an empty flag signal Empty when the control signal CO is not generated in response to the internal read clock signal iRCK.
FIG. 7 is a timing diagram illustrating the full flag signal generated from the flag generating circuit of FIG. 6. In particular, FIG. 7 shows the full flag signal generation timing diagram when the inverted write enable signal WEB (not shown) and the write clock signal WCK that are at a logic xe2x80x9clowxe2x80x9d level and the inverted read enable signal REB (not shown) and the read clock signal RCK that are at a logic xe2x80x9chighxe2x80x9d level are generated from an external portion.
The internal write clock signal iWCK is generated in response to the write clock signal WCK, and the write address WA is shifted in response to the internal write clock signal iWCK, so that all write addresses from the first write address wm0 to the last write address wm(k1) are generated, and then the first write address wm0 is generated again. At this time, the read address rmo and the write address wm0 become equal, so that the control signal CO is generated. The full flag signal Full is generated by the control signal CO generated in response to the internal write clock signal iWCK.
However, since the flag generating circuit of the conventional FIFO memory device generates the full flag signal Full by comparing the current write address with the current read address, there is a problem in that an interval TFull between a write clock signal generating time and a full flag signal generating time point is long.
FIG. 8 is a timing diagram illustrating the empty flag signal generated from the flag generating circuit of FIG. 6. In particular, FIG. 8 shows the empty flag signal generation timing diagram when the inverted read enable signal WEB (not shown) and the write clock signal WCK that have a logic xe2x80x9clowxe2x80x9d level and the inverted read enable signal REB (not shown) and the read clock signal RCK that have a logic xe2x80x9clowxe2x80x9d level are generated from an external portion. Also, in FIG. 8, the read clock signal RCK is faster in clock cycle than the write clock signal WCK.
The internal write clock signal iWCK is generated in response to the write clock signal WCK, and the write address WA is generated in response to the internal write clock signal iWCK. The internal read clock signal iRCK is generated in response to the read clock signal RCK, and the read address RA is generated in response to the internal read clock signal iRCK. When the write address wm(kxe2x88x928) is generated, and the read address rm(kxe2x88x928) is generated, the control signal CO is generated. At this time, the control signal CO is generated as the empty flag signal Empty in response to the internal read clock signal iRCK.
However, since the flag generating circuit of the conventional FIFO memory device generates the empty flag signal Empty by comparing the current write address with the current read address, there is a problem in that an interval TEmpty between a read clock signal generating time and an empty flag signal generating time point is long.
That is, the flag generating circuit of the conventional FIFO memory device generates flag signals after the current write address or the current read address is generated and thus is not suitable for a high-speed system.
To overcome the problems described above, the present invention provides a FIFO memory device having an advanced flag signal generating time point. The invention also provides a method of generating flag signals in a FIFO memory device that can advance a flag signal generating time point.
Accordingly, the present invention is directed to a FIFO memory device. The device of the invention includes a write address generating means generating a write address in response to a write clock signal. A read address generating means generates a read address in response to a read clock signal. A memory cell array includes a plurality of memory cells arranged between a plurality of write and read word lines and a plurality of write and read bit lines, the memory cell array storing write data in response to the write address and outputting read data in response to the read address. A flag signal generating means compares a next write address with a current read address to generate a full flag signal in response to the write clock signal when the next write address and the current read address are equal, and compares a current write address with a next read address to generate an empty flag signal in response to the read clock signal when the current write address and the next read address are equal.
The present invention further provides a method of generating a flag signal. The method includes providing a FIFO memory device including a plurality of memory cells arranged between a plurality of write and read word lines and a plurality of write and read bit lines, the plurality of memory cells storing write data in response to a write address and outputting read data in response to a read address. The write address is generated in response to a write clock signal and the read address is generated in response to a read clock signal. A next write address is compared with a current read address to generate a full flag signal in response to the write clock signal when the next write address and the current read address are equal, and a currrent write address is compared with a next read address to generate an empty flag signal in response to the read clock signal when the current write address and the write read address are equal.